1. Field of the Invention
The present invention concerns a filter circuit arrangement for filtering a radio-frequency signal with a tunable circuit and a phase regulation loop in order to hold the tunable filter to a constant transmission phase relative to the frequency of the radio-frequency signal.
2. Description of the Prior Art
In many technical fields, high-quality radio-frequency signal sources, whose signal frequencies can be adjusted in small steps (i.e. virtually continuously), are necessary in a number of applications. A typical example is local oscillators in receivers and transmitters in communication technology. For example, specific lower and upper frequency limits, an optimally low frequency step width and an optimally high step speed with simultaneously high adjustment precision and constancy of the set frequency, are among the requirements for such a radio-frequency signal source. Moreover, normally a minimal phase noise interval dependent on the frequency interval from the carrier as well as a minimal interference signal interval is specified that may not be under-run. Signal sources that operate according to the principle of direct digital synthesis (DDS) are particularly suitable for such applications in which very small frequency step widths are required. Direct digital synthesis is a technique in which digital data processing blocks are used in order to produce a highly precise clock pulse source with fixed frequency relative to a frequency- and phase-adjustable output signal. In essence, the reference clock pulse within the DDS architecture is thereby sub-divided with a division factor that is stored in a programmable, binarily adjustable word. The data word is typically 24 to 48 bits wide, and the output signal can be adjusted with an extraordinarily high frequency resolution with such a DDS module. For technical reasons, however, the resolution of the phase accumulator output is limited to a practical data word width in available DDS modules. Only a specific number of the higher-value bits of the data word is processed and the lower-value bits are ignored. A more or less significant amplitude error thus arises in each output value of a DDS system. Since this error sequence cyclically repeats in a periodic output signal, discrete interference lines (which are typically also designated as “spurious signals” often appear in the frequency spectrum of the DDS output signal. The amplitude and frequency position of these interference signals are dependent on the present data word with which the step width of the accumulator (and thus the frequency of the output signal) is established. Such spurious signals can lead to disruptions in the appertaining application in which the DDS system is used as a local oscillator. For example, if (as an oscillator) a frequency mixer of a transmitter is controlled with a DDS signal, unwanted ancillary emissions can occur. In reverse, unwanted ancillary reception points can arise at the receiver side given use of a DDS signal as a local oscillator signal. Given a use of DDS signals as local oscillators in a medical imaging method, this can also lead to artifacts, for example.
In the ADI application document, “Direct Digital Synthesis (DDS) Controls Waveforms in Test, Measurement and Communications” (analog.com/library/analogDialogue/archives/39-08/dds_apps.pdf), a hybrid architecture in which the reference signal input is fed from a DDS module to a phase regulation loop (also designated in the following as a “phase locked loop” or “PLL” for short) is described under the chapter “Fine-tunable reference for a PLL”. A rough frequency selection by adjustment of the divisor factor in the PLL feedback path is possible with this hybrid system. Fine frequency steps can be adjusted with a very high resolution via specification of the DDS frequency. For the reference signal the phase regulation loop thereby acts like a bandpass with double the bandwidth of the loop filter. The signal-to-noise ratio of spurious signals whose frequency interval relative to the reference signal is greater than the loop bandwidth of the phase regulation loop consequently increases due to the filter effect. Due to the multiplicative frequency conversion by the factor N, however, the interference signal interval within the PLL decreases by 20·log(N) [dB], such that the signal-to-noise ratio for interference signals is also reduced by this value within the regulatory loop bandwidth. Given the dimensioning of the bandwidth of the regulatory loop and of the reference frequency, a compromise is to be entered into with regard to noise performance, switching speed and interference signal suppression. Spurious signals outside of the tuning range of the DDS can in fact be suppressed via a fixed bandpass filter arranged downstream of the DDS. Spurious signals lying within the DDS tuning range pass the filter unattenuated.
A further variant in which the DDS signal is mixed with the feedback signal of the PLL is described in the same document. This variant is designated as an offset PLL. Here as well the high frequency resolution of DDS can be utilized. However, since the output signal of the mixer initially runs through a splitter with the divisor N before it arrives in the phase detector input of the phase regulation loop, the effect of the (in principle) decrease of the signal-to-noise ratio described above is compensated. However, the output signal is charged with additional noise due to the mixing process. Spurious signals within the filter bandwidth or within the loop filter bandwidth appear with unchanged level offset relative to the carrier on the output signal of the phase regulation loop.
Another possibility for generation of an optimally good reference signal (in particular as a local oscillator signal) is proposed in DE 10 2005 024 624. In the system described there a quartz oscillator operated in a regulated oven (what is known as an “oven-controlled oscillator; OCXO) is used and the output signal of this OCXO is then conducted through a phase-regulated filter circuit arrangement of the aforementioned type. A frequency multiplier is arranged downstream of the phase-regulated filter circuit arrangement. This design is shown in FIG. 1, whereby the basic principle of such a phase-regulated filter is presented using this example. An essential component of the phase-regulated filter circuit arrangement 1 is a filter module 5, here a quartz filter with variable center frequency. This tunable filter 5 is tuned within the phase regulation loop 4 such that the center frequency of the filter 5 can follow an input signal drifting in terms of frequency. Components of this phase regulation loop 4 are typically: a desired (target) actual value comparator or, respectively, phase comparator 6 (also often called a phase detector), here in the form of a multiplication element 6; a downstream integral regulator 7; and a low-pass filter 8. The principle functions such that the signal coming from the oscillator 2 is directed to the input of the detuneable filter 5, and to the phase comparator 6 as a reference signal (i.e. as a desire signal). The output signal coming from detuneable filter 5 is likewise fed back to the phase comparator 6 as a real signal or feedback signal. The output signal of this phase comparator 6 is dependent on the phase difference between the output signal of the filter 5 and the input signal of the filter circuit arrangement. A control signal is correspondingly generated in the integral regulator 7 and downstream low-pass filter 8, which control signal is provided to the control input 9 of the detuneable 5 in order to appropriately correct the filter 5.
The outgoing signal is then passed to the frequency multiplier 3, which generates the desired local oscillator signal. Such a corrected filter on the basis of a phase regulation loop does in fact have the advantage that the center frequency of the filter automatically follows the wandering frequency of the input signal, but a problem is that the capture range of the phase regulation loop stands in direct correlation to the bandwidth of the employed filter 5 within the filter arrangement 1. The capture range also shrinks with dropping bandwidth. The frequency range in which the phase regulation loop can be tuned to the corresponding input frequency is hereby designated as a capture range. If, during a tuning process of the phase regulation loop to the filter edge, the input signal is located far removed from the current filter center frequency of the filter 5, the level of the fed-back signal is not sufficient for an operation of the phase detector 6. The regulation can therefore not tune or “capture” or “lock”. The capture range can in fact be enlarged by increasing the bandwidth of the filter 5 used in the filter circuit is increased, but this has the disadvantage that the filter circuit arrangement no longer filters as well, and also that spurious signals lying further removed from the center frequency can pass through the filter. For this reason the filter circuit arrangement is not suitable for applications in which a large selection on the one hand and a large capture range on the other hand are required. The design of a circuit arrangement for generation of a local oscillator signal adjustable in a wider frequency range (for example with a DDS as an oscillator) is thus not possible with this filter circuit arrangement.
A further phase-regulated tracking filter is described in U.S. Pat. No. 6,420,916. In this design the problem also exists that, given an input signal whose frequency lies far outside the current set (via the variable center frequency) through-pass band, the amplitude of the fed-back signal is not sufficient in order to let the loop lock.
A tracking filter that has as a frequency-selective function block a low-pass filter bank connected to an N-path filter is disclosed in DE 23 63 387. In order to achieve a decoupling of filter capture range and filter bandwidth/quality, it is proposed to bridge the filter bank in the unlocked state via a detour path. The attenuation of the detour path is regulated via the amplitude of the output signal. The minimal attenuation of the detour path is selected such that on the one hand the amplitude of the output signal is sufficient to let the filter lock, but the signal amplitude at the output of the detour branch is distinctly smaller than at the output of the filter bank in the locked state. The attenuation in the detour path is successively increased with increasing output level. In the locked state the detour path is regulated so as not to be traversed. This particular type of capture range expansion is limited, however, to the specific application with N-path filters (since the transmission phase of the detour path for the locking process of the filter hereby remains unconsidered) and is not suitable for a usage with classical LC filters. However, N-path filters exhibit known, serious disadvantages relative to classical LC filters.
In the article “Dual bandwidth loop speeds-phase lock” by A. T. Anderson et al. in Electronics, 1975 Jan. 9, p. 116 to 117, a PLL is described in which selection can be made between two different loop paths. By a suitable execution of the cross-over switch it is achieved that the change-over from one loop path to the other path is optimally smooth. The cross-over to a lower bandwidth occurs after the locking of the PLL. Since in such a design the VCO monitoring voltage must possess a direct voltage portion, in principle the loop filters must exhibit a low-pass behavior. Therefore only the loop bandwidth (i.e. the upper limit frequency) of the low-pass filter is changed by the described arrangement. The design is thus not suitable for high-frequency bandpass filters.